1. Field
The present disclosure pertains to the field of information processing, and more particularly, to the field of error detection and correction in information processing systems.
2. Description of Related Art
Personal computer and other information processing systems often include mechanisms for detecting, and sometimes correcting, errors in information being transmitted or stored. These mechanisms may involve the generation of parity bits or error-correcting-code (ECC) bits based on a number of data bits, and the concatenation of these parity or ECC bits with the data bits prior to transmission or storage. Following transmission or storage, an operation may be performed on the data bits along with the parity or ECC bits to generate a “syndrome” that may indicate whether one or more of the data bits has been corrupted, and if so, which data bit or bits have been corrupted. Corrupted data bits may be inverted to correct the data.
Various techniques may be used for error correction and detection. Generally, a trade-off exists between the number of parity or ECC bits per data bit and the level of error correction and detection that is possible. Therefore, different techniques may be used for different applications. Selection of an appropriate technique may depend on an evaluation of cost versus reliability.